Layout Design, Staff Engineer

Responsibilities

• Lead physical layout development for embedded SRAM memory compiler peripheral circuits, including sense amplifiers, decoders, write drivers, and control logic across advanced technology nodes
• Optimize SRAM layouts to meet specifications for performance, power consumption, area efficiency, reliability, manufacturability, and yield
• Drive physical verification closure including DRC, LVS, ERC, antenna checks, and parasitic extraction, coordinating with CAD and verification teams to resolve technical issues
• Collaborate with circuit design teams to ensure layout implementations satisfy timing, matching, and electrical requirements
• Address advanced-node layout challenges including device matching, parasitic management, high-density routing, and reliability constraints
• Develop and implement layout methodology improvements and automation capabilities to enhance team productivity
• Provide technical guidance and mentorship to layout engineers, conducting design reviews and supporting skill development
• The Impact You Will Have
• Your layout implementations will directly influence the performance, power, and area characteristics of SRAM compilers integrated into customer system-on-chip designs
• The methodologies and automation capabilities you develop will improve development efficiency and reduce time-to-market for future memory compiler releases

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