Analog Design, Staff Engineer

Responsibilities

• Generate and validate IBIS models for DDRn, LPDDRn, HBM, and UCIe memory interface IP products, ensuring compliance with industry standards
• Develop timing characterization data and customer-facing timing collateral for board-level design and signal integrity analysis
• Extract behavioral models from transistor-level simulations and correlate them against silicon characterization results across PVT corners
• Work with analog design teams to capture circuit behavior and ensure models reflect real silicon performance
• Debug model discrepancies, timing violations, and signal integrity issues reported by customers or internal validation teams
• The Impact You Will Have
• Enable customers to successfully integrate Synopsys memory interface IP into their SoCs with accurate, reliable timing and IBIS models
• Reduce customer support escalations and silicon respins by catching model inaccuracies before tape-out
• Accelerate time-to-market for advanced memory products by streamlining the characterization and model release process
• Improve model quality and consistency across DDR, LPDDR, HBM, and UCIe product families through rigorous validation

Languages

Nice to have

• Experience with scripting languages like Python, Perl, or Tcl for automation is a strong plus
• You work well with cross-functional teams including circuit designers, layout engineers, and applications engineers who depend on your models

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