Layout Design, Sr Engineer

Responsibilities

• Design and implement full-custom layout for SRAM memory macros in advanced technology nodes, from bitcell to array to peripheral circuits
• Optimize layouts for area, performance, and power while maintaining design rule compliance and manufacturability
• Run and resolve DRC, LVS, ERC, Antenna, Density, and EM checks using Calibre, ICV, and other verification tools
• Collaborate directly with circuit designers to translate schematics into physical layouts that meet electrical and reliability specifications
• Work with process and foundry teams to interpret and apply technology files, design rules, and device models
• Iterate on layout based on parasitic extraction results and post-layout simulation feedback
• The Impact You Will Have
• Your layouts will directly determine the area efficiency, speed, and power consumption of SRAM macros used across Synopsys IP portfolios
• Optimized layout work you deliver will enable faster time to market for customers designing chips in leading-edge nodes
• Clean DRC/LVS closure you achieve will reduce tapeout delays and prevent costly respins

Languages

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