Layout Design, Manager

Responsibilities

• Lead a team of SRAM memory layout engineers through the full development cycle, from initial floorplanning and resource allocation to physical verification signoff and product release
• Own layout execution for memory arrays, bitcells, peripheral circuits, power distribution networks, and complete memory instances, ensuring they meet PPA, reliability, and manufacturability targets
• Drive resolution of complex physical design challenges including DRC, LVS, ERC, antenna violations, EM/IR analysis, routing congestion, and parasitic extraction issues across advanced FinFET and GAA nodes
• Manage project schedules, resource allocation, technical dependencies, and risk mitigation across multiple concurrent memory compiler and embedded memory development efforts
• Collaborate directly with circuit design, memory architecture, characterization, CAD tool development, physical verification, process technology, and foundry engineering teams to align layout execution with product requirements
• Build and improve layout methodologies, automation scripts, design reuse frameworks, and standardization practices that increase team efficiency and reduce development cycle time
• Mentor engineers, establish technical best practices, conduct performance reviews, support hiring and onboarding, and grow the technical capability of the layout organization
• The Impact You Will Have
• Deliver embedded SRAM memories and memory compiler products that meet aggressive PPA targets and enable customer tapeouts on schedule
• Reduce layout development cycle time and improve design quality through methodology improvements, automation, and reuse strategies that scale across multiple projects

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