SOC Engineer, Senior Staff

Responsibilities

• Leading block-level and chip-level physical design activities from netlist through final implementation (RTL to GDSII).
• Driving floorplan: block shaping, power planning, pin and macro placement, special routing and ESD considerations to meet customer requirements
• Placement, clock tree synthesis, post cts and routing optimizations for timing, power, area, congestion and signal integrity to meet stringent project requirements.
• Signoff timing, EMIR and physical verification analysis and closure with ECOs
• Partnering with cross functional (RTL, Implementation, DFT, packaging, foundation IPs, MBIST) teams to achieve hardening closure goals.
• Developing and improving automation scripts and methodologies to increase physical design efficiency and quality.
• Investigating and resolving design, tool, flow and machine issues throughout the implementation cycle.
• Mentoring junior engineers and providing technical leadership across the team.
• The Impact You Will Have
• Ensuring successful hardening of complex SOC subsystems projects and testchip tapeouts on schedule.

Languages

Nice to have

• Excellent written and verbal communication skills in English.
• Demonstrated ability to work effectively in cross-functional teams and build strong network relationships.
• Analytical and detail-oriented, with a strong problem-solving mindset.
• You are a passionate, detail-oriented engineer who thrives in collaborative and fast-paced environments. Your expertise in ASIC physical design makes you a go-to resource for solving complex challenges in silicon implementation. You enjoy mentoring others and sharing your knowledge, contributing to the technical growth…

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