SOC Engineering Intern

Responsibilities

• Supporting chip-level physical design activities from netlist through final implementation (RTL to GDSII)
• Gaining hands-on experience with key physical design stages, including floorplanning, placement, clock tree synthesis, routing, and physical verification.
• Assisting with design optimization for timing, power, area and congestion
• Contribute to debugging design or flow issues under guidance from senior engineers
• Supporting the development and improvement of automation scripts and design methodologies.
• Learning to investigate and troubleshoot design, tool, and flow-related issues throughout the implementation cycle.
• Participating in technical discussions, reviews, and knowledge-sharing activities within the team.

Languages