Senior Physical Design Engineer

Responsibilities

• You will lead all aspects of physical design and implementation of SOC devices targeted at the networking markets.
• Work will be at the partition and chiplet level.
• As a member of a team, you will participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
• Daily work involves all aspects of physical chip development (RTL2GDS) – trial synthesis, power and clock distribution, place and route, timing closure, power and noise analysis and physical verification.
• What we need to see
• BSEE / MSEE or equivalent experience.
• 5 years of experience in VLSI physical design implementation on 5nm, 4nm and 3nm technology.
• A successful track record of delivering designs to production is a requirement.
• Able to assist in design flow development and debugging, including application of ML/AI solutions.
• Already a validated strong power user of P&R, Timing Analysis, Physical Verification, IR Drop Analysis, CAD tools from Synopsys (ICC2/DC/PT/STAR/ICV), Cadence (Genus/Innovus/Tempus) and other major EDA companies.

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