Senior Silicon Validation Methodology Engineer - Low Power

Responsibilities

• Own architecture, design, and first-use of end-to-end LPWR validation methodology from silicon to product, covering corners, edge conditions, variability, and real-world scenarios.
• Set the department standard for LPWR validation so it is reused across a broad array of silicon products.
• Define what needs to be tested, why, and how — including coverage bounds, PVT/variability, test-time vs. schedule, signoff criteria, milestone playbooks, and SOL(speed of light) expectations.
• Invent and land new LPWR validation approaches that go beyond extending an existing test plan. Challenge current paradigms on performance, power, idle vs. active behavior, and corner-case coverage, and drive the resulting methods, tools, and metrics into org default practice.
• Set LPWR validation strategy and policy across teams, including long-lead items that outlive a single execution cycle.
• Translate architecture and product goals into multi-generation methodology, infrastructure, and tool investments.
• Drive cross-functional consensus with Architecture
• Design, Firmware, and Software under conflicting PPA, coverage, latency, and schedule priorities.
• Improve validation workflow at department scale by building and adopting automation, coverage metrics, pre-silicon to post-silicon correlation, and AI-enabled analysis. Fold learnings back into methodology, spec, and design.
• What we need to see

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