Senior Full-Chip RTL Integration Engineer

Responsibilities

• Lead RTL integration of multiple internal and third-party IPs into complex ASIC/SoC designs, owning top-level connectivity, clocking, reset architecture, address mapping, and power domain integration.
• Work closely with Architecture, RTL
• Design, Verification, DFT, and Physical
• Design teams to drive system-level integration and design closure.
• Perform RTL quality checks including lint, CDC, RDC, synthesis, and connectivity validation.
• Develop and carry out integration-level verification plans using SystemVerilog/UVM, debug simulation failures, and support functional coverage closure.
• Collaborate with DFT teams to integrate scan, MBIST, LBIST, JTAG, and other test structures, and review ATPG reports and fault coverage metrics to ensure testability requirements are met.
• Support design signoff activities and ensure smooth handoff across implementation stages.
• Develop automation and scripting solutions to improve integration, verification, and debug productivity.
• What we need to see

Languages