ASIC Physical Design Engineer, Netlisting - New College Grad 2026

Responsibilities

• Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks,…
• Help in ECO generation and implementation.
• What we need to see
• Master's or PhD degree in Electrical or Computer Engineering (or equivalent experience).
• Shown knowledge in logic equivalence checking/Formal Verification required from RTL to tapeout with industry-standard tools.
• Understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
• Experience in clock-domain-crossing checking, MTBF analysis, either with EDA tools (i.e., Synopsys or Cadence) or in-house tools.
• Background with logic synthesis at either block or full-chip level, at project execution and/or flow development.
• In-depth knowledge of industry standard EDA tools in related fields.
• Experience in programming and scripting languages, such as, Perl, TCL, Make, Python, etc.

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