Senior Package Layout Engineer

Responsibilities

• As part of a IC Packaging design team, you will collaborate to implement high speed and PDN design for ASIC packages.
• Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution using Cadence APD (Allegro) or SiP tools.
• Optimize package pin out incorporating system level trade-offs of pins assignment.
• Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.
• In close co-operation with the SI/PI/HW design teams and product teams
• Planning, ensuring stakeholder management and leading projects from start to finish
• What we need to see
• B.Sc. Electrical Engineering or an Electrical Practical Engineer certificate or equivalent experience
• 5+ years hands-on in Package/PCB Layout and outing experience; including high speed design signal integrity practices.
• Experience in substrate layout of wire bond and flip chip packages, preferred

Languages