Senior / Principal RTL & Embedded Security Firmware Engineer

Responsibilities

• Design and RTL Ownership
• Design, implement, and maintain FPGA fabric RTL for a multi-device secure platform, including device configuration, core separation, and security-monitor logic.
• Integrate third-party and internal IP cores (post-quantum crypto accelerators, SHA-3 / Keccak, JTAG and SPI programming cores) and bring them up on real hardware.
• Own the high-speed serial link between devices, including the hardware layer and its authenticated, encrypted full-duplex data path.
• Drive synthesis, place-and-route, timing closure, and resource optimization.
• Define and evolve RTL coding standards, review practices, and design methodology.
• Security Hardware Mechanisms
• Define and implement physical attack detection (tamper) mechanisms and the corresponding response actions.
• Design and implement zeroization logic and its verification, per ISO 19790 requirements.
• Define and implement the secure, certifiable update scheme for FPGA fabric, bootloader, and firmware images, including self-programming / in-application programming flows.

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