Manager, Silicon Circuit Co-Design - Silicon Co-Design Group

Responsibilities

• Lead a team of senior engineers across silicon bring-up, post-silicon validation, and circuit co-design for NVIDIA's safety, reliability, and performance enhancement features — including the noise, dI/dt, and power integrity challenges that determine whether those features hold under real operating conditions across…
• Set technical direction. Define how the team characterizes circuits, closes simulation-to-silicon gaps, quantifies noise and dI/dt margins, analyzes aging and reliability mechanisms, triages failures, and drives fixes to confirmation. Your methodology is what scales across programs and generations.
• Own the hard calls. When a reliability circuit isn't holding its margin, when a dI/dt transient is coupling into a sensitive feature, when substrate or supply noise is the hidden variable behind a failure that looks like something else, when a production program is at risk — you are in the room, and your judgment is…
• Hire and develop outstanding engineers.
• Build a team with depth in circuit co-design, power integrity, noise characterization, reliability physics, and post-silicon validation. Make the people around you measurably better.
• Drive cross-functional alignment. Your team sits at the intersection of circuit design, architecture, VLSI, PDN, reliability engineering, firmware, and product. You ensure that intersection produces decisions, not delays.
• What we need to see
• BS or MS in Electrical Engineering, Computer Engineering, or equivalent.
• 10+ overall years in silicon validation, circuit co-design, or post-silicon characterization, with at least 3 years leading technical teams.
• Deep circuit fundamentals — analog, digital, mixed-signal — with genuine expertise in power integrity, noise analysis, dI/dt characterization, and reliability and aging mechanisms. Deep enough to earn the respect of the engineers you lead and challenge the conclusions they bring you.

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