Senior Full Chip Layout and Physical Verification CAD Engineer

Responsibilities

• You will be in charge of developing full-chip physical design methodologies, Physical Verification development and support through all the projects, Tapeout activities for implementation of networking chips and SOCs.
• Work closely with Full Chip Layout owners and block owners, project managers to assure high quality and timely convergence.
• Come up with unique and creative solutions to the state of the art FCL physical design problems that are needed for our chips.
• We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.
• Participating and developing flow and tool methodologies for fullchip, physical design verification across multiple projects.
• What we need to see
• B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).
• You should have at least 5+ years of hands-on Full-chip layout and Physical Verification experience, demonstrating your proven expertise.
• A strong background in Physical Verification methodology, including DRC / LVS / ANT / ERC / DFM in advanced process nodes is necessary.
• Proficiency using Python, Tcl, Shell, Make scripting.

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