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ASIC Digital Design, Sr Engineer

Synopsys

Armenia · On-siteSalary not disclosedfull-timeSynopsys Careers
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You are an ASIC digital designer who has taken RTL modules from specification through implementation and into production silicon. You write timing-aware Verilog, and you use synthesis, timing, and power results to improve your designs.

Responsibilities

  • Design and own RTL modules for UCIe Controller IP, from microarchitecture through synthesis-ready implementation, with guidance from senior designers
  • Tune your modules to meet timing, power, and area targets, and incorporate feedback from synthesis and timing analysis across process nodes
  • Develop Python, Tcl, and Perl scripts for design generation and flow integration
  • Participate in design reviews and contribute improvements to team methodology
  • The Impact You Will Have
  • Your modules will ship in UCIe IP used in high-volume HPC, automotive, and AI products
  • You will help deliver a core Synopsys product line while building depth in controller and high-speed interface design

Languages

    Work format
    On-site
    Seniority
    Senior
    Posted
    20 Oct 2026
    Last verified
    In the last 3 days

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