ASIC Digital Design, Sr Staff Engineer

Responsibilities

• Design RTL modules for UCIe Controller IP from microarchitecture through synthesis-ready implementation
• * Optimize designs to meet timing, power, and area targets across multiple process nodes
• Develop Python/tcl/perl automation for design generation and flow integration
• Collaborate with cross-functional teams to resolve timing and power challenges
• Contribute to design reviews and methodology development
• The Impact You Will Have
• * Your designs will enable UCIe IP deployed in high-volume HPC, automotive, and AI products
• * You will contribute to a solid revenue-generating product line for Synopsys
• * Your work will define performance characteristics for customer systems-on-chip
• * Your automation will improve design efficiency across the engineering team

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