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ASIC Digital Design, Sr Staff Engineer
Synopsys
Armenia · On-siteSalary not disclosedfull-timeVerified recentlySynopsys Careers
You work effectively across organizational boundaries, collaborating with architecture, verification, and physical design teams. You manage technical tradeoffs systematically, balancing performance, area, and power requirements while maintaining schedule commitments.
Responsibilities
- Design RTL modules for UCIe Controller IP from microarchitecture through synthesis-ready implementation
- * Optimize designs to meet timing, power, and area targets across multiple process nodes
- Develop Python/tcl/perl automation for design generation and flow integration
- Collaborate with cross-functional teams to resolve timing and power challenges
- Contribute to design reviews and methodology development
- The Impact You Will Have
- * Your designs will enable UCIe IP deployed in high-volume HPC, automotive, and AI products
- * You will contribute to a solid revenue-generating product line for Synopsys
- * Your work will define performance characteristics for customer systems-on-chip
- * Your automation will improve design efficiency across the engineering team
Languages
- Work format
- On-site
- Seniority
- Senior
- Posted
- 16 Sept 2026 (yesterday)
- Last verified
- 17 Sept 2026