Chip Level Defect Localization and Failure Analysis Engineer - RDSS Intern

Responsibilities

• Your main job will be to perform electro-optical failure analysis including Photon-Emission, Laser-Voltage-Probing and Soft-Defect-Localization (aka SDL, LADA...) to support product development, design-debug, yield-ramp, reliability and customer return analysis of advanced flip chip devices manufactured in the most…
• The work requires in-depth understanding of scan-chain based logical test. Based on production test results (e.g. error-logs, flop mapping and SW-diagnosis) you will narrow down the logically failing area with the goal of locating the one failing FET or cell out of the whole chip.
• Most analyses will require you to setup test-loops within our Advantest 93k tester SW. Additionally, you will use CAD layout tools for in-chip navigation and circuit simulation tools to aid your analysis. The goal is that our EFA results enable different Physical FA teams local and abroad to find the actual physical…
• You will need basic Unix skills because the CAD, circuit simulation tools and 93k tester SW are all run in a Unix environment.
• Design-debug and more complicated defect localizations will often require you working in multi-functional teams (e.g. with
• Design for Test, Test-Engineers and Product-Engineers, sometimes around the globe..) including presenting & explaining your results. To guide such team and PFA efforts you will need deep understanding of transistor physics, the CMOS fabrication processes and PFA tools/techniques such as SEM, TEM, FIB & AFM.
• Support Die Probe Package second-source development for A16 FA readiness.
• What we need to see
• Master's or PhD degree in Electrical/Computer Engineering or other related field
• Basic understanding of DFT for large-scale logical test (scan-chain based structural and at-speed testing and basics of test compression).

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