Senior Analog Layout Design Engineer

Responsibilities

• Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools
• You will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
• Job duties will include floor planning, custom layout and verifying against design rules and schematics, EM/IR analysis
• What we need to see
• You will have a minimum of 5 years of relevant mask analog layout experience
• An Electronics Practical Engineer certificate or a B.Sc. in Electrical Engineering
• Proven understanding of analog circuit layout concepts in submicron CMOS and FinFet technologies - such as Operational Amplifiers and ADC/DACs.
• You are an expert with Cadence custom circuit design tools - particularly Virtuoso
• Experience running and debugging DRC and LVS with verification tools such as ICV, Calibre
• You can work effectively in a team, good interpersonal skills, enthusiasm and positive energy.

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