DFT Engineer - Hardware

Responsibilities

• As a member in our team, you will be responsible for end-to-end DFT from RTL design to Gate level scan insertion to Verification (including JTAG, boundary scan, security mechanisms, and test clocking—across various test modes, including multiple ATPG configurations) to silicon bring-up.
• Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.
• In addition, you will help develop and deploy DFT methodologies for our next generation products.
• Be apart of innovation to strive improve the quality of DFT methods.
• You will also need to work with multi-functional teams to incorporate DFT features into the chip.
• Occasional travel and also some late hours online meetings involved during critical milestones.
• What we need to see
• BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience
• You should be well versed with static timing Analysis, ECO, ASIC/Logic
• Design Flow, HDL and Digital logic design.

Languages