Formal Verification Engineer - New College Graduate 2026

Responsibilities

• Learning state-of-the-art formal verification methodologies
• Responsible for applying best-in-class formal methodologies on complex digital designs, IP blocks and SoCs
• Taking ownership of verifying a design by developing a robust test plan
• Executing it by working with the design team
• Coordinating with other verification team members for closure
• What we need to see
• B.Tech./ M.Tech in Electrical Engineering / Computer Science or related fields
• Strong analytical skills to solve difficult problems
• Understanding of abstraction techniques for effective verification
• Hands-on experience with HDLs such as Verilog / System Verilog

Languages