Principal Engineer, Package Integration and Manufacturability

Responsibilities

• Lead the technical assessment of package risk across our chip programs — identifying failure modes in substrate, interposer and assembly integration before they reach silicon, quantifying their cost and schedule impact, and bringing them to program and technology reviews with a clear position
• Drive new approaches to manufacturability across the board (package, substrate, interposer, silicon), spanning yield improvement, capacity and supply review, test strategy, thermal and assembly process maturity. Push co-design levers such as tolerance relaxation by design, testability before attach, design margins, and…
• Analyze module yield mechanics, reconcile predicted versus actual yield on units returning from assembly, and convert the findings into concrete design guidance
• Evaluate emerging packaging and photonics technologies, including outside partner solutions, and define our product requirements — working closely with our advanced technology group
• What we need to see
• B.S or M.S. in Electrical Engineering, Mechanical Engineering, Materials Science or equivalent experience
• More than 15 years of experience in package technology development or system integration, with multiple products carried through assembly
• Deep understanding of 2.5D, chiplet and organic substrate integration. Working knowledge of assembly and module yield mechanics, including how alignment tolerance and process excursions drive assembly yield differently from defect density at the die level
• Strong analytic capabilities, and passion for solving demanding technical problems
• Ability to drive complex activities involving many interfaces and teams, and to hold a technical position across organizations

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