Senior Mask Layout Design Engineer

Responsibilities

• Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools
• You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products and Job duties will include floor planning, custom layout and verifying against design rules and schematics.
• What we need to see
• Hold a BSEE or equivalent experience. MSEE is a plus.
• 8+ years of relevant mask design / layout experience
• Tape-out experience with FinFET technology is required. Experience with TSMC N5/N4/N3 is preferred.
• Experience with high-speed SerDes/RF layout design is helpful and Experience with top level integration would be excellent to have.
• Deep understanding of analog circuit layout concepts in submicron CMOS technologies
• Validated experience with Cadence custom circuit design tools - particularly virtuoso
• Experience running and debugging DRC and LVS with verification tools such as ICV/Calibre

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