Senior Signal Integrity Engineer - LPU Packaging

Responsibilities

• Lead signal integrity design and analysis for high-speed SerDes channels across die, package, board, connector, socket, and cable interfaces
• Develop and execute simulation flows for advanced packaging technologies, including 2.5D, 3D, and multi-die integration, with strong focus on channel loss, discontinuities, return path behavior, and crosstalk
• Build and optimize chip-package-board co-simulation methodologies for next-generation HPC and data center systems
• Drive SI modeling and design optimization for package escapes, vias, breakouts, interposers, substrates, sockets, and other critical channel structures
• Perform pre-layout and post-layout signal integrity analysis, create design guidelines, and review layouts to ensure electrical performance targets are met
• Correlate simulation with lab measurements using TDR, VNA, oscilloscope, and related measurement techniques to improve model accuracy and signoff confidence
• Work closely with ASIC, package, board, mechanical, thermal, and validation teams to co-optimize electrical performance across the full product stack
• Support interface bring-up, debug, and margin analysis, and help translate correlation learnings into improved design methods and reusable flows
• Automate analysis, data processing, and visualization to improve productivity and scale SI methodology across multiple programs
• What we need to see

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