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Lead Hardware Design Validation Engineer - Memory Subsystem
NVIDIA
US, CA, Santa Clara · On-site · relocation$14,000–26,833 gross/mofull-timeNVIDIA Careers (offices abroad)
What you will be doing: Hands-on leadership of HBM/GDDR enablement, validation, and failure analysis for NVIDIA’s datacenter and graphics products. Drive review of memory partner’s design limits and test methodology.
Responsibilities
- Drive review of memory partner’s design limits and test methodology. Integrate learnings into unique characterization and test plans for each memory generation.
Languages
- Work format
- On-site
- Seniority
- Lead
- Posted
- 9 Jul 2026
- Last verified
- In the last 5 days
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