ASIC Design Engineer, High Speed IO

Responsibilities

• As a designer, be responsible for understanding the specific protocol concepts and features, make architectural trade-offs based on feature/performance/power requirements, analyze system implications, come up with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon…
• During the course of a project you would end up driving the following aspects of design for your unit
• Own micro-architecture and RTL development of design modules
• Micro-architect features to meet performance, power and area requirements
• Work with HW architects to define critical features
• Partner with verification teams to verify the correctness of implemented features
• Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.
• What we need to see
• You should be BTech/MTech in EE, ECE or similar stream, having a proven track record with 2+ years of experience in crafting complex Units and CPU/micro-controller based Sub-systems
• Knowledge of HSIO standards, protocols and architectures of modern SOC's would be a significant plus

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