Senior ASIC Power Management Micro Architect, Chip Design

Responsibilities

• Owning the front-end micro-architecture and design of Power Management IP ASIC blocks, from the IP definition phase through the full design cycle and into post-silicon bring-up and enablement.
• Serving as a key player in the development and enablement of new power management technologies across NVIDIA's product lines.
• Delivering high-quality, synthesizable RTL as part of the IP Chip
• Design team.
• Partnering closely with architecture, verification, physical design, and validation teams to drive successful tape-out and silicon bring-up.
• Leading post-silicon debug, characterization, and enablement activities to bring your blocks from concept to working silicon.
• What we need to see
• BSc or MSc in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience).
• 12+ years of hands-on RTL design experience.
• Proven experience bringing a block from the development phase all the way through to post-silicon bring-up and enablement.

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