Senior Mixed Signal Design Engineer

Responsibilities

• Mixed-Signal/Analog circuit design for High Speed Memory I/O Interfaces
• Solve challenge of circuit designs in deep submicron CMOS FinFET processes
• Take designs through productization and be involved in all stages of development
• Work with multi-functional teams to optimize the designs
• What we need to see
• Advanced High-Speed
• Design Expertise: 5+ years of proven experience in high-speed memory (LPDDR, DDR, GDDR, HBM) or SerDes design, underpinned by a BSEE or MSEE and a deep understanding of system-level timing budgets and specifications.
• FinFET Circuit Mastery: In-depth technical command of deep submicron CMOS FinFET processes, with the ability to navigate complex circuit design challenges and implementation nuances.
• Reliability & Physical Integrity: Comprehensive knowledge of device reliability, ESD, and Latch-Up requirements, including the ability to supervise layout development to ensure strict adherence to these critical rules.
• Full-Flow Tool Proficiency: Expert-level command of Cadence custom design environments and industry-standard simulators (Hspice, XA, FineSim, Spectre), with a working knowledge of Verilog, Nanotime, or Matlab.

Languages