Software R&D Engineer, VLSI Physical Design - New College Grad 2026

Responsibilities

• Invent new optimization engines that fuse traditionally independent engines (e.g., co-optimization of legalization and sizing) with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools.
• Improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction.
• We as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.
• What we need to see
• Masters or PhD in Electrical Engineer or Computer Science (or equivalent experience).
• Experience with VLSI algorithms development using C++.
• Understanding of VLSI timing optimization and related concepts, including cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, congestion, etc.
• Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC and typical design flows written in Perl, Tcl, and Python.
• Ways to stand out from the crowd
• C++14 or newer experience, such as lambdas and concurrency.

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