Senior ASIC Design Engineer, GPU Core Pipeline IP

Responsibilities

• As a key member of our ASIC
• Design team, you will contribute to the design and implementation of graphics and compute features within an IP.
• You will be responsible for the micro-architecture and RTL design of GPU ASICs, working closely with architecture, verification and physical design teams to deliver high-quality designs.
• You will develop RTL using Verilog/SystemVerilog, collaborate on design specifications, and ensure that designs meet performance, power, area, and timing goals.
• Work with HW architects and designers to make the right implementation choices.
• Collaborate with verification engineers to ensure comprehensive validation and coverage of all implemented functionality.
• You will be working with architects, verification engineers, and other members of your design teams to accomplish your tasks.
• Participate in silicon bring-up, post-silicon debug, and performance analysis as needed.
• What we need to see
• B.Tech./ M.Tech. with 5+ years of relevant experience.

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