SOC Clocks RTL Design Engineer

Responsibilities

• Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-out
• Defining and implementing the SOC clock and reset architecture together with the micro-architecture team — collecting clocking requirements from every unit on the chip and turning them into a coherent, verifiable design
• Owning clock domain crossing infrastructure and CDC closure across the SOC
• Partnering with the micro-architecture team to review specifications, close on design intent, and provide feedback on implementation cost, timing, area, and power
• Working hand-in-hand with the Physical
• Design (backend) team on clock tree implementation and constraints, partitioning, floorplan and timing feedback, trial synthesis, congestion and timing convergence, and physical design readiness
• Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows
• Driving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checks
• Supporting SOC-level chip build and assembly, and developing/deploying automation flows that make RTL integration and design quality checking repeatable and scalable
• Supporting emulation, firmware, and post-silicon bring-up customers of your design

Languages