Senior Silicon Architect - Cache Coherent Interconnects

Responsibilities

• As a member of our core CPU team, you'll own the silicon architecture and construction plan for next-generation CPU processors.
• Explore 2D multi-chip module, 2.5D interposer and 3D hybrid-bonded dielet constructions, including the placement of IO and compute (CPU cores, caches and NOC) across dielets.
• Develop early floorplans, and plan die-to-die and off-chip IO, including UCIe, DRAM and PCIe.
• Work with architecture, logic design, physical design and packaging teams to achieve your area, performance, power and thermal goals.
• What we need to see
• Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
• 8+ years of experience in processor or other related high-performance semiconductor designs.
• Deep understanding of digital design, CPU system architecture and ASIC floor-planning, including wire densities on-die and across 3D connected dies.
• A strong background in cache coherency or high-speed interconnects and industry-standard coherency/IO/memory protocols is helpful.
• Knowledge of advanced packaging (TSMC InFO and CoWoS, Intel EMIB), through-silicon via configurations and backside power delivery is preferred, along with Dielet, Interposer, Substrate connectivity.

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