HSIO Validation Lead - Silicon Co-Design

Responsibilities

• Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness.
• Close the hardest failures.
• Drive root cause across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities and own every fix through to confirmation.
• Define validation strategy.
• Set test coverage, debug priorities, margining methodology, and stress criteria for each program. Your strategy is what stands between a silicon risk and a customer escape.
• Own and build AI agents that operate under your direction. These include automated debug triage, intelligent data pipelines, and analysis flows. They reduce cycle time and identify issues before production. Know where AI accelerates real work and where it introduces risk.
• Ensure robust interoperability across the full ecosystem: retimers, switches, accelerators, CPUs, GPUs, and sophisticated multi-device system topologies.
• Sit at the decision table. Your analysis drives alignment across architecture, logic design, circuit design, firmware, drivers, ATE, DGX, and product teams. Your data is what settles calls.
• Translate what you learn on real silicon into methodology and coverage improvements that make future products harder to escape.
• What we need to see

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