Senior Verification Engineer

Responsibilities

• Define verification scope, develop and drive testplans (functional and performance), and build scalable UVM-based infrastructure; leverage agentic AI to automate repetitive tasks, accelerate debug, and sharpen team efficiency.
• Develop UVM testbenches and checkers; work with C/C++-based testbenches and debug reference models and designs developed in HLS; track metrics and drive coverage closure.
• Critically reason through architectural solutions and partner with our architects to develop well-crafted, silicon-proven designs.
• Collaborate across NVIDIA sites globally and work closely with external partners and customers to deploy verification flows, ensure consistent display IP behavior across diverse tool stacks, and debug complex integration issues across organizational boundaries.
• What We Need to See
• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field (or equivalent experience)
• 10+ years of relevant experience.
• Strong hands-on expertise in UVM, SystemVerilog, Verilog, Python, and C/C++, with a passion for root-causing complex issues; experience with constrained-random stimulus, functional coverage, assertion-based verification, and C/C++-based testbenches — ideally on shipped silicon.
• Proficiency with industry EDA tools (VCS, Verdi/Debussy, GDB) and strong software engineering practices: clean, maintainable code; version control; code review.
• Domain knowledge of display pipelines: protocols (DisplayPort, HDMI, MIPI DSI/CSI), MMU interaction with ISO clients, and system low-power features (clock gating, power domains, retention, entry/exit sequences).

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