Senior ASIC Verification Engineer, Coherent High Speed Interconnect

Responsibilities

• Responsible for verification of high-speed coherent interconnect design, architecture, golden models, and micro-architecture using sophisticated verification methodologies.
• You'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), complete test/coverage plans, and verify the correctness of the design.
• Collaborate with architects, designers, emulation, and silicon verification teams to accomplish your tasks.
• What we need to see
• Bachelors or Master’s Degree (or equivalent experience).
• 5+ years of relevant verification experience.
• Experience in architecting test bench environments for unit level verification.
• Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies. Prior
• Design or Verification experience of Coherent high-speed interconnects.
• Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI will be useful.

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