Senior System Architect, High-Speed Interconnects

Responsibilities

• Architectural Definition
• Lead the end-to-end definition of high-speed interconnect systems for next-gen AI platforms (e.g., Rubin and beyond), focusing on 224G/448G PAM4 lanes and beyond.
• Technology Roadmap: Evaluate and select pioneering technologies such as Co-Packaged Optics (CPO), Silicon Photonics, and advanced OSFP/QSFP-DD form factors.
• System Co-Design
• Collaborate with ASIC, Thermal, and PCB teams to optimize the "Silicon-to-Connector" path, minimizing insertion loss and improving signal integrity.
• Standardization Leadership: Represent NVIDIA in industry standards bodies (e.g., IEEE 802.3, OCP, MSA) to influence the future of high-speed connector and cable specifications.
• Vendor Ecosystem: Work with world-class connector and cable vendors to drive custom mechanical and electrical designs that meet NVIDIA's unique performance requirements.
• Performance Modeling
• Conduct trade-off analyses between reach, power, latency, and cost for various interconnect media (Copper vs. Optical).
• What we need to see

Languages