Senior AI Verification Chip Design Engineer

Responsibilities

• AI Ecosystem Development
• Build and deploy an AI verification environment, moving from manual testbenches to automated stimulus generation and coverage closure.
• Next-Gen Tooling
• Develop and integrate AI agents and ML models directly within the verification toolchain to automate intent-to-testbench workflows.
• Intelligent Debugging
• Create and refine AI-based debug assistants that can analyze simulation failures, categorize bugs, and suggest fixes autonomously.
• Methodology Innovation
• Research and apply groundbreaking AI approaches (such as Reinforcement Learning or LLMs) to address the "state-space explosion" in chip verification.
• Collaborative Intelligence: Work with design automation teams and EDA vendors to ensure our AI solutions provide end-to-end efficiency from RTL to GDS.
• Leadership & Training

Languages