ASIC Physical Design Engineer - New College Graduate

Responsibilities

• Chip integration and netlist generation
• Synthesis, RTL/netlist quality check and formal verification
• Constraints creation and validation, timing budget.
• Work with ASIC team to analyze/resolve special timing issues as well as cross-team collaboration to implement chip partitioning and floorplan
• Work in conjunction with PR engineers to achieve timing closure for both partition and full chip level
• Achieve special mode timing closure, such as io, test, clock, async etc.
• Function eco creation
• Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout)
• Flow automation development for above areas
• Methodology in any of above areas.

Languages