Senior Physical Verification Engineer

Responsibilities

• Own physical verification closure for major blocks or full-chip designs through tapeout.
• Lead debugging of complex DRC, LVS, and reliability-related issues and drive high-quality resolution.
• Define verification check plans, signoff criteria, and closure priorities with cross-functional teams.
• Partner with physical design, custom design, and CAD teams to improve quality and turnaround.
• Drive automation, methodology improvements, and best practices for scalable PV execution.
• Review results, coach team members, and help reduce repeated classes of violations.
• What we need to see
• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.
• 5+ years of experience in physical verification, backend implementation, or ASIC signoff.
• Deep knowledge of DRC, LVS, physical signoff methodology, and tapeout flows.

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