Senior STA Engineer

Responsibilities

• Drive static timing analysis and timing closure for block and/or full-chip designs.
• Develop, review, and debug timing constraints, scenarios, and signoff checks.
• Analyze setup, hold, noise, and variation-related timing issues and drive closure with cross-functional teams.
• Partner with physical design engineers on floorplan, CTS, route, ECO, and convergence activities.
• Review reports, identify root causes of violations, and recommend high-quality fixes with minimal design impact.
• Improve timing methodology, automation, and debug efficiency using Tcl, Perl, and/or Python.
• What we need to see
• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.
• 5+ years of experience in ASIC or SoC physical design, timing analysis, or implementation.
• Strong understanding of static timing analysis fundamentals, timing constraints, and timing closure.

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