Senior Design Verification Engineer - GPU Memory Subsystem

Responsibilities

• Actively collaborate with RTL, DV, FV, and Arch teams to then develop and implement design verification strategies for our GPU ASIC memory subsystem IP.
• Perform functional and performance verification using advanced tools and methodologies. Bring your innovative ideas to the table.
• Gain a deep understanding of this critical IP's micro-architectural design and implementation while continuing to advance your verification skills.
• What we need to see
• BS Degree in CompE, EE, CS, or equivalent experience
• 5+ years of experience covering the full scope of pre-silicon ASIC verification, including the development of verification strategy, test plans, tests, testbench components, regression triage, debug, and coverage closure and experience with industry standard tools
• Working knowledge of computer architecture fundamentals and their constructs in Verilog/System Verilog
• Ways to stand out from the crowd
• Strong analytical thought process and outstanding debug skills.
• Experience with caches, coherency, complex pipelines, arbiters, or interconnect networks

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