Senior ASIC Design Engineer - Clocks IP

Responsibilities

• As a Clocks team member, you will be architecting the clock domain to satisfy functional, physical and testing design requirements.
• Engage with multiple teams and design the GPU or CPU clocks to satisfy all the architectural/design/physical constraints.
• Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.
• Collaborate with Physical design and timing team to evaluate Clocking concerns and develop solutions for supporting high speed Clocking.
• Together with other team members, we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams.
• Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
• What we need to see
• BS in Electrical Engineering or equivalent experience (MS preferred)
• 3+ years of relevant work experience.
• Deep understanding of logic optimization techniques and PPA trade-offs.

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