Principal Chip Lead, Silicon Co-Design Group

Responsibilities

• You will partner across design, validation, software, and manufacturing to keep the program’s technical narrative clear and on track. Day to day, you will
• Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs.
• Co-lead program-level feature integration from chip to system, surfacing inter-function dependencies and guiding them to resolution.
• Help resolve the program’s hardest multi-functional bugs by translating ambiguous, multi-team symptoms into root-cause closure on areas such as HBM, power and thermal, high-speed I/O, and packaging.
• Steward the qualification playbook. When the playbook does not fit a situation, guide the mitigations and capture the lessons as reusable methodology for other SSG programs.
• Shape the program’s technical narrative by surfacing key risks, trade-offs, and mitigations as decision-ready options for executive leadership.
• Mentor Chip Leads on adjacent silicon programs and contribute to SCG-wide methodology through post-mortems and write-ups.
• Lead the program’s Critical Debug and SCG Technical Execution forums, and represent the chip externally with early insight into technical risks.
• What we need to see
• BS or MS (or equivalent experience) in Electrical or Computer Engineering, plus over a decade of proven track record in post-silicon bring-up, validation, or system integration leadership at a major semiconductor company, including work on multiple shipped silicon products.

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