Senior ASIC Verification Engineer - HSIO

Responsibilities

• Be responsible for the verification of ASIC design, architecture, golden models and micro-architecture of High Speed I/O controllers, like Ethernet and NVLink, at IP/sub-system levels using advanced DV methodologies such as UVM.
• Building reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
• Understanding the design specification and implementation, defining the verification scope, developing test plans, tests, and the verification infrastructure used to verify the correctness of the design.
• Collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
• What we need to see
• Bachelors or Masters Degree (or equivalent experience) with 5+ years of relevant experience
• Experience at Unit/Sub-system/SOC level and expertise in SystemVerilog, UVM
• Expertise in comprehensive verification of IP or interconnect protocols (e.g. Ethernet, USB, SATA)
• Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies (UVM) and exposure to industry standard verification tools for simulation
• Excellent debugging, analytical, and problem solving skills

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