Low Power ASIC Engineer - New College Grad 2027

Responsibilities

• Working very closely with Low Power Architecture
• Design, and Software teams to understand next generation features.
• Responsible for architecting/developing testbench, infrastructure, and testplans to verify various power management solutions for NVIDIA products.
• You will have the opportunity bring creative ideas that help improve power-aware DV methodologies, as well as influence EDA vendors to improve our simulation and debug efficiencies.
• What we need to see
• Recently completed a BS, MS or PhD in Electrical or Computer Engineering, or equivalent experience.
• You have an understanding of low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling (DVFS) etc.
• Good understanding of processor architecture (GPU is a plus), and related power management design/DV techniques.
• Must be experienced with Incisive Low-Power or Synopsys VCS NLP
• Strong debug skills and experience with Verdi is needed

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