Senior DFT Engineer

Responsibilities

• Design and roll out advanced test methodologies on NVIDIA’s next-generation silicon platforms.
• Own and work with cross-functional teams to implement the latest in test access mechanisms, IO BIST, memory BIST, and scan compression.
• Collaborate closely with VLSI and Product Engineering groups to design innovative DFT approaches that advance silicon test technology.
• Lead end-to-end planning and timely execution of NVIDIA's new chip bring-up efforts, from pre-silicon through production deployment.
• Develop and standardize methodologies, processes, and workflows for silicon bring-up, crafting reusable checklists and playbooks.
• Improve cross-team communication, work, and handoffs.
• Guide and mentor junior engineers, helping them navigate complex build trade-offs to achieve world-class quality and efficiency.
• What We Need To See
• BSEE (or equivalent experience) with 5+ years, MSEE with 3+ years, or PhD in DFT or related domains.
• Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG, and fault simulation.

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