Senior Verification Engineer - Audio and Auxiliary CPU Sub-Systems

Responsibilities

• You will develop UVM-based verification test benches and methodologies for unit level, write verification components and API's for cluster and system level test benches. These will verify dedicated CPU sub-systems targeted for Audio processing, Functional Safety, RAS, BOOT and power management.
• During the course of a project, you will drive the following aspects of verification for your unit
• Architect the testbenches and craft verification environment using SV, UVM and C/C++ methodology
• Define test plans, tests and verification infrastructure for clusters and systems
• Build efficient and reusable bus functional models, monitors, checkers, scoreboards, API's and encapsulated components
• Implement functional coverage and own unit, cluster and SOC level verification closure
• Work with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust and feed back and bug escapes driven improvements to your setup
• What we need to see
• BTech or MTech in ECE, EE, CSE, or an equivalent degree is required. Candidates should have over 5 years of experience in verification closure of complex units, sub-systems, or SOC level verification.
• Proven experience in RISCV, ARM or DSP core based CPU sub-systems.

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