Senior Physical Design Methodology Engineer, PPA Improvement Technology Scaling

Responsibilities

• Developing physical design methodologies for implementation of graphics processors and SOCs.
• Key responsibility includes developing unique and creative solutions to the state of the art physical design problems that are needed for NVIDIA chips.
• Participate in PPA experiments for testing and developing new technologies for CPUs/GPUs including running chip floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.
• Develop Automation to solve early design collaterals, for eg. developing scripts for analysis of new library cells, scripts for modifying design constraints for new technologies
• What we need to see
• MS in Electrical or Computer Engineering (or equivalent experience)
• Minimum 5 years’ experience in Physical
• Design Engineering
• Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.
• Experience with Physical

Languages