Senior Software R&D Engineer, VLSI Physical Design

Responsibilities

• Invent new optimization engines that fuse traditionally independent engines (e.g., co-optimization of legalization and sizing) with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools. These tools already outperform the industry's alternatives in…
• Improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction.
• As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.
• What we need to see
• BS, MS, PhD or equivalent experience in Electrical Engineering or Computer Science
• 6+ years in VLSI algorithms development using C++
• Strong understanding of VLSI timing optimization and related concepts, including cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, congestion, etc.
• Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC and typical design flows written in Perl, Tcl, and Python
• Strong communication and interpersonal skills
• Ways to stand out from the crowd

Languages