Senior Silicon Power Engineer

Responsibilities

• Lead the effort across architecture, validation, firmware, software, and production teams to keep the program's power and low-power productization strategy clear, executable, and on track.
• Characterize and validate new power-saving features, debug silicon issues, and work with SW/FW teams to productize industry-defining capabilities.
• Resolve complex silicon issues through structured hypotheses, measurement plans, and root-cause closure — and codify the fixes as reusable methodology across programs.
• Design and deploy AI-enabled workflows to automate data analysis, metric extraction, trend checks, and report generation across multiple bring-ups — with explicit guardrails and measurable workflow impact.
• Serve as the key technical owner for multi-functional decisions, issues, and tradeoffs across power, thermal, performance, firmware, and schedule constraints.
• Partner with globally distributed teams — system architects, chip and board designers, SW/FW engineers, applications, reliability specialists, ATE engineers, and PMs — including counterpart engineers in India and other major hubs.
• What we need to see
• BS + 5 years, or MS + 4 years, in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience), with a proven track record in post-silicon bring-up and validation of silicon power features on complex ASIC or SoC programs.
• Deep hands-on expertise in power-saving mechanisms, power characterization, tester-to-system correlation, and lab fundamentals (oscilloscopes, DMM, DAQ, debuggers) — with at least one specific example of taking an ambiguous power failure to root-cause closure with a productized fix.
• Strong end-to-end understanding of silicon behavior across architecture, firmware, validation, and platform interactions, and a demonstrated ability to make sound tradeoff decisions across power, thermal, performance, firmware, design, validation, and schedule constraints.

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