ASIC Verification Engineer - New College Grad 2027

Responsibilities

• Employ cutting edge AI technologies to create automated systems and flows
• Contribute to complex UVM testbench environments including test development, automation, or analysis
• Develop directed or random tests in SystemVerilog to verify the reference C++ and RTL models in a simulation environment
• Debug RTL simulation failures
• What we need to see
• Pursuing or recently completed a BS, MS, or PhD in EE, CE, or related field (or equivalent experience)
• Coursework or prior internship exposure to computer architecture, logic design, and/or HDL languages (Verilog, VHDL)
• Strong programming experience in C++ or SystemVerilog and general understanding of OOP concepts
• Solid understanding of basic concepts of CPU or SoC architecture.
• Exceptional analytical skills and problem solving skills

Languages